Outside Associates for:
Robotic Pick and Place System
Debugged client's new old stock supply of Staubli RX-60 industrial robotic arms. Designed, coded, and implemented system to automate the pick and place process, moving parts from trays to tape and reel. This was implemented with an RX-60 arm and end-effector using a pneumatic suction cup as one tool and a pneumatic gripper on the other side to move trays. All electrical, mechanical, and pneumatic design, construction, and test were performed by the author. Staubli RX-60 arms for sale.
Machine Vision System
System design and test of a machine vision system for detecting electrical components having bent leads as an add on feature to a manual high speed taper. Performed lens selection and distortion analysis, lighting selection and modification, all mechanical and electrical design. System design for tolerance of lighting variations and improved reliability of detection. This system is used in conjunction with the above pick and place system.
Video Encoder Core Design
System and detailed design of a
video encoder offered as a drop in integrated circuit core product.
This design accepts CCIR601 digital data in and outputs analog video
compatible with industry standard monitors.
Microprocessor Consultation for
Supported development of a 200,000 gate quad Ethernet controller design for a major communications company. This chip was fabricated in submicron technology and was successful in first silicon.
Detailed design of an ASIC controller for a two-way set associative copy back cache memory. This ASIC provides the second level cache for a fault tolerant RISC CPU (R3000) card. A top down design methodology was used which included: VHDL (IKOS VOYAGER), gate level synthesis (SILCSYN), acceleration (IKOS), and emulation (Quickturn). First pass success in both emulation and silicon.
Investigated high level synthesis tools capable of accepting behavioral VHDL as input.
Requirements analysis, architectural, and detailed design of precision time maintenance and high speed interface card. The final architecture included three custom (standard cell) VLSICs and a microcontroller.
Refined the DSP sub-system architecture for a prototype spread spectrum communications system. 15 parallel processors were used in the final design providing a peak throughput of 300 MFLOPS. Responsible for processor throughput analysis, host computer control interface protocol, and hand coded DSP microcode, met timing by one clock, the code was tight.
Reviewed new design plan and was instrumental in increasing CPU performance upgrade target from 2X speed to 3X. Recommended the use of instruction prefetch, main memory cache, and a two-stage pipeline. Completely responsible for design and simulation of complex pipeline control logic using a unique configuration of field programmable logic. This configuration avoided the need for a costly custom gate array, which was believed to be needed but was not provided for in the design budget. Received Pride and Excellence in Performance Award for this work.
Detailed architecture and design of an FPU to increase customers CPU performance 10X for math intensive applications. Analyzed various methods for implementation.
Manager of this experimental super computer project.
Host/Control Computers - DIGITAL VAX11/780, 4 - PDP11/34s
Custom High Speed Processor - 4 parallel, microcoded, very long instruction word, pipelined processors with hardware arithmetic (floating point) and data base hardware.
Data Routing Array - Data path switch with 18 64 bit data paths.
Central Working Storage - 4 banks of high speed pipelined static memory.
Mass Storage - 2 Master disk controllers and 10 slave triported controllers for parallel control of 20 Winchester disk drives.
Performed detailed architecture and hardware design, prototype test, integration, microcode definition and generation for 3D graphics transformation algorithm. Designed and implemented application program software interface, low level software driver and test software. This system included a dedicated pipelined scene memory and a microcoded custom floating point processor. The system was controlled by an RMX based MULTIBUS control computer. This system is used for flight simulation by various air force bases.
Developed a lower cost parallel processor approach for 3D and area graphics generation. The suggested approach utilized floating point DSP and RISC microprocessor components to quadruple performance, simplify programming, and reduce costs.
Analyzed and corrected major digital design flaws involving transmission line effects, timing, and noise margin problems in real time area graphics and video subsystems, which caused manufacturing delays potentially leading to contract default. Systems were efficiently delivered by incorporating these design improvements. Redesigned analog video section.
Developed I/O subsystem upgrade, using a 68020 microprocessor and dual port RAM to quadruple I/O performance. The new architecture provided reduced cost, improved performance, SCSI and LAN interfaces.
Analysis of timing and protocol problems identified cards not complying with the MULTIBUS specification. Worked with OEM and Customer engineers to correct these problems, which resulted in improved production rate by streamlining the previously slow and problematic final test.
US 6,473,801 System and Method for
M. Eng. E.E. Cornell University
B.S.E.E. Worcester Polytechnic Institute
Eta Kappa Nu Honor Society
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